High voltage laterally diffused metal oxide semiconductor (LDMOS) transistors are used in power management, microwave and RF power amplifiers, for example. LDMOS devices use Metal-Insulator-Silicon (MIS) surfaces and back-channel field plates to assist in depletion of the drift region, allowing more charge to be placed into the drift region, and thereby reducing on-resistance and on-state power dissipation.
Planar LDMOS devices (devices without STI) can result in superior reliability performance due to the absence of field and current crowding at STI corners; however, in known conventionally fabricated planar LDMOS devices, gate-to-drain capacitance is high, compared to an STI based device. Also, there is a fundamental tradeoff between low conduction losses (on-resistance or Rsp) and switching losses (Qgg and Qgd) and off-state breakdown voltage.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.